Sub-60nm Si tunnel field effect transistors with Ion >100 µA/µm

Author

Loh, Wei-Yip ; Jeon, Kanghoon ; Kang, Chang Yong ; Oh, Jungwoo ; Patel, Pratik ; Smith, Casey ; Barnett, Joel ; Park, Chanro ; Liu, Tsu-Jae King ; Tseng, Hsing-Huang ; Majhi, Prashant ; Jammy, Raj ; Hu, Chenming

Author_Institution

SEMATECH, Austin, TX, USA

fYear

2010

fDate

14-16 Sept. 2010

Firstpage

162

Lastpage

165

Abstract

Si-tunneling field effect transistors (TFETs) with a record I_on >100 μA/μm and high I_on/I_off ratio (> 10⁵) at V_ds=1V are reported. Using an optimal spike and millisec flash anneal coupled with an engineered source-gate overlap through a gate-last process, Si TFETs have been demonstrated with 10 to 1000 times greater current than previously reported. The devices exhibit negative differential resistance and temperature dependencies consistent with band-to-band tunneling and current characteristics in excellent agreement with 2D TCAD simulations.

Keywords

elemental semiconductors; field effect transistors; silicon; technology CAD (electronics); tunnel transistors; 2D TCAD simulations; Si; band-to-band tunneling; gate-last process; millisec flash anneal; negative differential resistance; optimal spike; silicon TFET; silicon tunnel field effect transistors; source-gate overlap; temperature dependency; voltage 1 V; Annealing; Current measurement; Logic gates; Semiconductor process modeling; Silicon; Temperature measurement; Tunneling;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Device Research Conference (ESSDERC), 2010 Proceedings of the European

Conference_Location

Sevilla

ISSN

1930-8876

Print_ISBN

978-1-4244-6658-0

Type

conf

DOI

10.1109/ESSDERC.2010.5618418

Filename

5618418