• DocumentCode
    2805837
  • Title

    Substrate bias dependency of sense margin and retention in bulk FinFET 1T-DRAM cells

  • Author

    Collaert, N. ; Aoulaiche, M. ; De Keersgieter, A. ; De Wachter, B. ; Jurczak, M. ; Altimime, L.

  • Author_Institution
    Imec, Heverlee, Belgium
  • fYear
    2010
  • fDate
    14-16 Sept. 2010
  • Firstpage
    154
  • Lastpage
    157
  • Abstract
    The substrate bias in bulk FinFET devices can be used to increase both the sense margin and retention time in 1T memory cells. For given biasing conditions, a substrate bias can be found where sense margin and retention time are optimal. This substrate bias results from a trade-off between the storage of electrons and holes and the impact of the READ conditions.
  • Keywords
    MOSFET; random-access storage; substrates; 1T memory cells; READ conditions; bulk FinFET 1T-DRAM cells; bulk FinFET devices; retention time; sense margin; substrate bias dependency; Charge carrier processes; Electric potential; FinFETs; Logic gates; Random access memory; Steady-state; Substrates;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Device Research Conference (ESSDERC), 2010 Proceedings of the European
  • Conference_Location
    Sevilla
  • ISSN
    1930-8876
  • Print_ISBN
    978-1-4244-6658-0
  • Type

    conf

  • DOI
    10.1109/ESSDERC.2010.5618428
  • Filename
    5618428
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2805837