On Channel Modeling for Impulse-Based Communications over a Microprocessor´s Power Distribution Network

As the complexity of a modern microprocessor increases rapidly, the methods of testing/debug take up increasing silicon area and create a cumbersome routing problem. The core power distribution network (PDN) of a microprocessor supplies power to a majority of underlying circuits. In this paper, we propose to explore use of the PDN in a microprocessor as a communication channel for test/debug purposes. Although, there are some common characteristics with power line communications (PLC) over power grid in a residential network, PLC over a PDN is very different in channel characteristics, tolerance to voltage fluctuations and noise characteristics. Further, decoupling capacitors attached to the package and the PDN of a microprocessor makes the PDN a bulky low pass filter. However, it is well known that the parasitic inductance of a decoupling capacitor is more significant beyond the self resonant frequency, and our measurements on an Intel microprocessor indicates that the low pass filter becomes leaky at higher frequencies beyond 1 GHz. In this work, measurements are used to model the PDN of a microprocessor as a communication channel and estimate the path loss characteristics as well as the channel impulse response. Link budget is calculated for the proposed communication system and receiver design considerations are derived. Measurement results and power supply noise analysis indicate that the use of jitter-robust pulse shapes, spread-spectrum techniques and strong coding would be required to communicate reliably over the PDN of a microprocessor.