• DocumentCode
    2806150
  • Title

    How detrimental could a via be?

  • Author

    Shan, Lei ; Kwark, Young ; Dreps, Daniel ; Trewhella, Jean

  • Author_Institution
    Thomas J. Watson Res. Center, IBM Corp., Yorktown Heights, NY, USA
  • fYear
    2004
  • fDate
    25-27 Oct. 2004
  • Firstpage
    91
  • Lastpage
    94
  • Abstract
    The vertical interconnects used in printed circuit boards, known as vias, are becoming increasingly critical to interconnect performance with ever increasing system data rates. To explore the effects of vias on system link performance, both simulations and measurements on test structures were implemented in a wide frequency range. The results indicate that proper via management is vital to the success of interconnect designs operating at multi-Gb/s data rates.
  • Keywords
    interconnections; notch filters; printed circuit design; printed circuits; notch filters; printed circuit boards; system data rates; system link performance; test structures; vertical interconnect design; vias management; Degradation; Geometry; Insertion loss; Integrated circuit interconnections; Packaging; Printed circuits; Reflection; Resonance; Solid modeling; System performance;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electrical Performance of Electronic Packaging, 2004. IEEE 13th Topical Meeting on
  • Print_ISBN
    0-7803-8667-1
  • Type

    conf

  • DOI
    10.1109/EPEP.2004.1407555
  • Filename
    1407555