A system solution to reducing frequency of memory repairs

Author

Chen, C.L. ; Hsiao, M.Y.

Author_Institution

IBM Corp., Poughkeepsie, NY, USA

fYear

1997

fDate

15-16 Dec 1997

Firstpage

53

Lastpage

58

Abstract

Single symbol error correcting and double symbol error detecting (SSC-DSD) codes have been used in m-bit-per-chip computer memories for fault-tolerance and for savings in repair costs. In this paper, we present a solution to the reduction of memory repair actions for memories designed with SSC-DSD codes. We present a scheme that extends the basic SSC-DSD scheme to the data recovery of double symbol errors. We also make a comparison on reliability improvements in terms of frequency of repairs for different coding systems

Keywords

error correction codes; error detection codes; fault tolerant computing; memory architecture; system recovery; SSC-DSD codes; coding systems; data recovery; double symbol error detecting codes; double symbol errors; fault-tolerance; frequency reduction; m-bit-per-chip computer memories; memory repairs; reliability improvements; single symbol error correcting codes; system solution; Circuits; Costs; Decoding; Error correction; Error correction codes; Fault tolerance; Frequency; Processor scheduling; Read-write memory; Scheduling algorithm;

fLanguage

English

Publisher

ieee

Conference_Titel

Fault-Tolerant Systems, 1997. Proceedings., Pacific Rim International Symposium on

Conference_Location

Taipei

Print_ISBN

0-8186-8212-4

Type

conf

DOI

10.1109/PRFTS.1997.640125

Filename

640125