DocumentCode
2806198
Title
Quantifying Thread Vulnerability for Multicore Architectures
Author
Oz, Isil ; Topcuoglu, Haluk Rahmi ; Kandemir, Mahmut ; Tosun, Oguz
Author_Institution
Comput. Eng. Dept., Bogazici Univ., Istanbul, Turkey
fYear
2011
fDate
9-11 Feb. 2011
Firstpage
32
Lastpage
39
Abstract
Continuously reducing transistor sizes and aggressive low power operating modes employed by modern architectures tend to increase transient error rates. Concurrently, multicore machines are dominating the architectural spectrum in various application domains. These two trends require a fresh look at resiliency of multithreaded applications against transient errors from a software perspective. In this paper, we propose and evaluate a new metric called the Thread Vulnerability Factor (TVF). A distinguishing characteristic of TVF is that its calculation for a given thread (which is typically one of the threads of a multithreaded application) does not depend on its code alone, but also on the codes of the threads that share data with that thread. As a result, we decompose TVF of a thread into two complementary parts: local and remote. While the former captures the TVF induced by the code of the target thread, the latter represents the vulnerability impact of the threads that interact with the target thread. We quantify the local and remote TVF values for three architectural components (register file, ALUs, and caches) using a set of four multithreaded applications. Our experimental evaluation shows that TVF values tend to increase as the number of cores increases which means the system becomes more vulnerable as the core count rises. We also discuss how TVF values and execution cycles together can be used to explore performance-reliability tradeoffs in multicores at a source code level.
Keywords
computer architecture; multi-threading; multiprocessing systems; reliability; multicore architecture; multicore machinesTVF; multithreaded application; performance reliability; software perspective; thread vulnerability; thread vulnerability factor; transient error; Benchmark testing; Hardware; Instruction sets; Multicore processing; Registers; TV; Transient analysis; Fault tolerance; Reliability; multithreading;
fLanguage
English
Publisher
ieee
Conference_Titel
Parallel, Distributed and Network-Based Processing (PDP), 2011 19th Euromicro International Conference on
Conference_Location
Ayia Napa
ISSN
1066-6192
Print_ISBN
978-1-4244-9682-2
Type
conf
DOI
10.1109/PDP.2011.75
Filename
5738979
Link To Document