Analog Front-End ASIC Requirements for a FDM Broadband Powerline System Enabling Co-Existence

This paper presents a feasible set of analog ASIC requirements optimized to achieve co-existence in a broadband power line communications (PLC) system based on frequency division multiplexing (FDM). FDM is the most straightforward way to achieve co-existence between different systems, however, this involves many design challenges at the circuit level. First, a short description will be given of the PLC system, which is under development in the EU funded IST POWERNET project. It will be shown that conventional receiver architectures, typically designed for time division multiple access (TDMA) schemes, are not well suited for FDM systems e.g. due to challenges arising from near/far situations. Solutions to improve the performance will be discussed and simulation results will be presented of the proposed architecture, based on parameters extracted from circuit designs, to show the feasibility of high bit rates in FDM transceivers.