DocumentCode :
2806448
Title :
Accelerating Parameter Sweep Applications Using CUDA
Author :
Motokubota, Masaya ; Ino, Fumihiko ; Hagihara, Kenichi
Author_Institution :
Grad. Sch. of Inf. Sci. & Technol., Osaka Univ., Suita, Japan
fYear :
2011
fDate :
9-11 Feb. 2011
Firstpage :
111
Lastpage :
118
Abstract :
This paper proposes a parallelization scheme for parameter sweep (PS) applications using the compute unified device architecture (CUDA). Our scheme focuses on PS applications with irregular access patterns, which usually result in lower performance on the GPU. The key idea to resolve this irregularity is to exploit the similarity of data accesses between different parameters. That is, the scheme simultaneously processes multiple parameters instead of a single parameter. This simultaneous sweep allows data accesses to be coalesced into a single access if the irregularity appears similarly at every parameter. It also reduces the amount of off-chip memory access by using fast on-chip memory for the data commonly accessed for multiple parameters. As a result, the scheme achieves up to 4.5 times higher performance than a naive scheme that processes a single parameter by a kernel invocation.
Keywords :
combinatorial mathematics; computer graphic equipment; coprocessors; information retrieval; optimisation; parallel architectures; CUDA; GPU; compute unified device architecture; data access; irregular access pattern; off-chip memory access; on-chip memory; parallel architecture; parameter sweep application; Acceleration; Graphics processing unit; Instruction sets; Kernel; Memory management; Optimization; CUDA; GPU; acceleration; parameter sweep;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Parallel, Distributed and Network-Based Processing (PDP), 2011 19th Euromicro International Conference on
Conference_Location :
Ayia Napa
ISSN :
1066-6192
Print_ISBN :
978-1-4244-9682-2
Type :
conf
DOI :
10.1109/PDP.2011.19
Filename :
5738992
Link To Document :
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