• DocumentCode
    2806901
  • Title

    Scheduling as Rule Composition

  • Author

    Dave, Nirav ; Pellauer, A. ; Pellauer, Arvind

  • Author_Institution
    Comput. Sci. & Artificial Intell. Lab., Massachusetts Inst. of Technol., Cambridge, MA
  • fYear
    2007
  • fDate
    May 30 2007-June 2 2007
  • Firstpage
    51
  • Lastpage
    60
  • Abstract
    Bluespec is a high-level hardware description language used for architectural exploration, hardware modeling and synthesis of semiconductor chips. In Bluespec, one views hardware as a collection of stateful elements (e.g., registers, memories) and describes its behavior using rules, or Guarded Atomic Actions which modify these elements. All legal behaviors of a Bluespec program can be explained in terms of rules being applied in some sequence. Scheduling is the process of selecting which rules to execute in parallel while maintaining this semantic invariant. The scheduling decision can have a large impact on critical design properties such as pipeline concurrency and clock frequency. What constitutes a good schedule of en depends upon the application and requires the designer´s input. In this paper we introduce BTRS, the kernel language for Bluespec and use it to explore the task of scheduling. We view scheduling as the process of restricting a Bluespec design´s non-deterministic behavior to be deterministic. We define a small set of scheduling operators whose semantics are expressed in terms of rule composition. We show how to represent the schedules generated by the Bluespec compiler using these compositions. More importantly, our scheduling primitives open a large class of new schedules which are needed for microarchitectural explorations.
  • Keywords
    concurrency control; hardware description languages; pipeline processing; scheduling; Bluespec program; clock frequency; guarded atomic actions; high-level hardware description language; pipeline concurrency; rule composition; scheduling; Clocks; Concurrent computing; Frequency; Hardware design languages; Kernel; Law; Legal factors; Microarchitecture; Pipelines; Registers;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Formal Methods and Models for Codesign, 2007. MEMOCODE 2007. 5th IEEE/ACM International Conference on
  • Conference_Location
    Nice
  • Print_ISBN
    1-4244-1050-9
  • Type

    conf

  • DOI
    10.1109/MEMCOD.2007.371249
  • Filename
    4231772