Search-Space Optimizations for High-Level ATPG

Author

Campos, Jorge ; Al-Asaad, Hussain

Author_Institution

Dept. of Electr. & Comput. Eng., California Univ., Davis, CA

fYear

2005

fDate

Nov. 2005

Firstpage

84

Lastpage

89

Abstract

The mutation based validation paradigm (MVP) is a validation environment for high-level microprocessor implementations. To be able to efficiently identify and analyze the architectural states (prospect states) that can possibly satisfy a set of constraints during MVP´s test generation, the authors need to reduce the search space in the analysis process as early as possible. In this paper, the authors present some optimizations in the search space that speed up the overall test generation process

Keywords

automatic test pattern generation; high level synthesis; microprocessor chips; MVP test generation; architectural states; high-level ATPG; high-level microprocessor; mutation validation paradigm; search-space optimizations; set of constraint; validation environment; Automatic test pattern generation; Boolean functions; Computational modeling; Computer simulation; Data mining; Debugging; Logic testing; Microprocessors; Sequential analysis; Test pattern generators;

fLanguage

English

Publisher

ieee

Conference_Titel

Microprocessor Test and Verification, 2005. MTV '05. Sixth International Workshop on

Conference_Location

Austin, TX

ISSN

1550-4093

Print_ISBN

0-7695-2627-6

Type

conf

DOI

10.1109/MTV.2005.23

Filename

4022233