Title :
Impact of low-K wire bond stacked flip chip CSP package material on reliability test
Author :
Tsung-Shu Lin ; Wang, Chen-hsiao ; Lin, Joe ; Chen, K.M.
Abstract :
As the consumer electronics market expands, system-in-package (SiP) has become more popular in recent years. By stacking different dies with different functions in a single package, SiP has benefits for space efficiency and flexibility of integrating functions. With die stacking, bi-material interfacial delamination becomes a prime concern of reliability testing. This paper presents an evaluation of molding compound and underfill material for wire bond stacked flip chip CSP (WBSFCCSP). The test vehicle size is 16mm x 16mm x 1.2mm with a 4mm x 5mm x 0.15mm low-K wire bond die stacked on a low-k 8mm x 8mmm x 0.15mm flip chip die. The reliability testing condition is JEDEC MSL2a (60degC/60%RH, 120hrs, reflow three times at peak temperature of 260degC) and 1000 cycles of thermal cycling test (TCT -55degC~125degC). The severe pre-conditioning environment makes the material selection become more challenging. Delamination between the underfill and other package components leads to premature failure. TCT stress also induces the interface of bottom die backside and encapsulated molding compound delamination. In this evaluation, the EMC selection was decided by the first stage experimental results based on the assembly yield. A design of experiments (DOE) performed by finite element analysis (FEA) was used to study the effect of underfill property on package stress. From FEA results, the underfill selection trend for solving underfill delamination and bottom die backside delamination is a conflict. Low coefficient of thermal expansion (CTE) and high Young´s modulus (E) underfill can reduce the stress at bottom die backside corner but increase the underfill pressure. In order to solve this conflict, plasma cleaning was applied before underfill dispensing to improve the underfill and package components interface bond strength. In the second stage experiment, three underfills were evaluated base on different reasons, low modulus to prevent underfill delamination, high modulus t- - o reduce bottom die backside stress and low moisture absorption to reduce steam pressure. Only the high modulus underfill can pass reliability testing.
Keywords :
Young´s modulus; chip scale packaging; delamination; design of experiments; finite element analysis; flip-chip devices; integrated circuit reliability; integrated circuit testing; lead bonding; moulding; thermal expansion; CSP package material; EMC selection; FEA; JEDEC MSL2a; SiP; Young´s modulus; bottom die backside delamination; chip scale packaging; design of experiments; finite element analysis; interface bond strength; low-k wire bond stacked flip chip package; molding compound delamination; plasma cleaning; reliability testing; system-in-package; thermal cycling test; thermal expansion coefficient; underfill delamination; underfill material; underfill property; Bonding; Chip scale packaging; Delamination; Electronics packaging; Flip chip; Materials reliability; Materials testing; Stacking; Thermal stresses; Wire;
Conference_Titel :
Microsystems, Packaging, Assembly and Circuits Technology, 2007. IMPACT 2007. International
Conference_Location :
Taipei
Print_ISBN :
978-1-4244-1636-3
Electronic_ISBN :
978-1-4244-1637-0
DOI :
10.1109/IMPACT.2007.4433560