A TDM Test Scheduling Method for Network-on-Chip Systems

Much current research has focused on employing network-on-chips (NoC´s) for communication among numerous cores on large scale SoC´s. One side benefit of such designs is the potential to utilize this communication infrastructure with little modification for manufacturing test delivery. In this paper the authors present a test scheduling approach for such designs that minimizes test time through high-speed test delivery over the network and lower rate test execution at the target cores. To achieve this, test data are interleaved over the network in a time division multiplexed (TDM) approach. Experimental results with the ITC´02 SoC benchmarks are proposed that show substantial test time reduction beyond single speed techniques. Further enhancements are presented that overcome some deficiencies in the simplest approach