Implementation of low jitter clock distribution using chip-package hybrid interconnection

As the clock frequency of digital systems goes higher up to multi-GHz, it is getting more important to distribute the clock signal to each destination with minimum timing jitter as not to exceed the timing margin of the system. For the lossy characteristic of on-chip interconnection lines, repeaters are indispensable to distribute the clock signal on a chip and the number of repeaters is increasing as clock frequency goes up for reliable signal quality. However, these kinds of repeaters can cause timing jitter on the clock signal when they are affected by power supply noise which is usually generated by logic core operation. This work shows a possible solution for the problem, that is, chip-package hybrid interconnection by which some repeaters are no longer necessary and verifies that the hybrid interconnection reduces clock jitter dramatically through implementation and measurement.