A study of material effects for the panel level package (PLP) technology

The wafer level package (WLP) is a cost-effective solution for electronic package, and it has been increasingly applied during recent years. In this study, a new packaging technology which retains the advantages of WLP, the panel level package (PLP) technology, is proposed to further obtain the capability of signals fan-out for the fine-pitched integrated circuit (IC). In the PLP, the filler material is selected to fill the trench around the chip and provide a smooth surface for the redistribution lines. Therefore, the solder bumps could be located on both the filler and the chip surface, and the pitch of the chip side is fanned-out. In our previous research, it was found that the lifetime of solder joints in PLP can easily pass 3,500 cycles. The outstanding performance is explained by the application of a soft filler and a lamination material. However, it is also learned that the deformation of the lamination material during thermal loading may affect the reliability of the adjacent metal trace. In this study, the material effects of the proposed PLP technology are investigated and discussed through finite element analysis (FEA). A factorial analysis with three levels and three factors (the chip carrier, the lamination, and the filler material) is performed to obtain sensitivity information. Based on the results, the suggested combinations of packaging material in the PLP are provided. The reliability of the metal trace can be effectively improved by means of wisely applying materials in the PLP, and therefore, the PLP technology is expected to have a high potential for various applications in the near future.