Title :
A model for on-chip decoupling capacitor effectiveness including gate leakage effects
Author :
Rius, Josep ; Meijer, Maurice
Author_Institution :
Dept. d´´Enginyeria Electron., Univ. Politecnica de Catalunya, Barcelona, Spain
Abstract :
This work presents a model for on-chip decoupling capacitors (decaps) including gate tunnelling current. The model shows that lumped models of decaps at high frequencies fail and have to be substituted by a distributed model. It also shows how the gate leakage reduces the effectiveness of such decaps for both, low and high frequencies.
Keywords :
MOS capacitors; MOS digital integrated circuits; integrated circuit modelling; leakage currents; MOS capacitor; distributed decoupling capacitor model; gate leakage effects; gate tunnelling current; lumped decoupling capacitor model; on-chip decoupling capacitor model; CMOS technology; Capacitance; Circuits; Equations; Gate leakage; Leakage current; MOS capacitors; MOSFETs; Tunneling; Voltage;
Conference_Titel :
Electrical Performance of Electronic Packaging, 2004. IEEE 13th Topical Meeting on
Print_ISBN :
0-7803-8667-1
DOI :
10.1109/EPEP.2004.1407616
