Solder bump oxidation prevention by fabricating thermal oxidation barrier layer of wafer level process

As of now, solder bump oxidation has been one of the concerns in the shelf period from wafer level bumping process to flip chip assembling. The issue has been confirmed as continuous enhanced oxidation due to the high temperature and/or high humidity storage environment. Such phenomenon causes the so-called "discolored bumps", which means darker solder ball surface can be observed by macro view due to the degradation on reflection of native oxide property. The effected bumps, including high lead (Pb-5 % Sn), eutectic (Pb-63 % Sn), and tin-silver (Sn-2.3 Ag) lead free systems, all show a thicker oxidation layer than as- reflowed ones, and they have a higher risk on non-wetting failure of flip-chip assembling reflow process. In this study, a specific thermal oxidation method has been introduced to fabricate a controlled quality oxidation layer right after reflow. The layer then acts as a barrier, which is able to prevent further native oxide growing in post storage period. From the Auger electron spectrum (AES) and depth analysis results, the purpose of the oxidation layer can be monitored and the prevention effect can be confirmed.