Title :
Low-Level VHDL Modeling of Digital-to-Analog Converter
Author :
Huang, Peng ; Teng, Daniel H Y ; Bolton, Ronald J.
Author_Institution :
Univ. of Saskatchewan, Saskatoon
Abstract :
This paper describes an approach to low-level VHDL modeling of digital-to-analog converter (DAC). A 12-bit DAC was modeled and simulated with Cadence NC-Sim simulator to test the feasibility of the approach. The simulation result shows that the approach can achieve faster simulation than circuit simulations with better accuracy than behavioral simulations.
Keywords :
circuit simulation; digital-analogue conversion; hardware description languages; Cadence NC-Sim simulator; VHDL modeling; behavioral simulations; circuit simulations; digital-to-analog converter; CMOS logic circuits; Circuit simulation; Computational modeling; Digital-analog conversion; Hardware design languages; Mirrors; Signal resolution; Software libraries; Switches; Switching circuits;
Conference_Titel :
Electrical and Computer Engineering, 2007. CCECE 2007. Canadian Conference on
Conference_Location :
Vancouver, BC
Print_ISBN :
1-4244-1020-7
Electronic_ISBN :
0840-7789
DOI :
10.1109/CCECE.2007.28
