• DocumentCode
    2809202
  • Title

    Constructucting method of VIP and VMM based SoC verification environment

  • Author

    Feng, Yan ; Chen, Lan

  • Author_Institution
    Inst. of Microelectron., Chinese Acad. of Sci., Beijing, China
  • fYear
    2011
  • fDate
    15-17 July 2011
  • Firstpage
    3965
  • Lastpage
    3968
  • Abstract
    VIP and VMM-compliant code are reusable both during a project and on later designs. This paper describes the constructing method of Synopsys´s VIP and VMM based SoC verification environment, and then takes the Interrupt Controller module as an example to present the designing method of derived environment. The functional coverage is 100% after simulating 90s. Finally, a traditional SoC verification environment was constructed for comparison. The comparison is based on the verification of Interrupt Controller module in the two environments. The result indicates that the traditional verification environment expends 2X code and 2.7X runtime compared to another. Thus it can be seen that the VIP and VMM based SoC verification environment presented in this paper is not only more flexible and reusable, but also helps achieve higher verification productivity while writing less code. Now the verification environment has been used in project.
  • Keywords
    formal verification; integrated circuit design; system-on-chip; SoC verification environment; VIP-compliant code; VMM-compliant code; constructing method; designing method; interrupt controller module; system on a chip; Generators; Hardware design languages; IEEE standards; IP networks; Manuals; Monitoring; System-on-a-chip; Reusable; System Verilog; VIP; VMM; Verification Environment;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Mechanic Automation and Control Engineering (MACE), 2011 Second International Conference on
  • Conference_Location
    Hohhot
  • Print_ISBN
    978-1-4244-9436-1
  • Type

    conf

  • DOI
    10.1109/MACE.2011.5987869
  • Filename
    5987869