Author :
Balasubramanian, Padmanabhan ; Edwards, D.A. ; Narayanan, C. Hari
Abstract :
In the domain of combinational logic synthesis, simplification of functions based on AND-OR logic is a well studied area. However, since many real-life combinational functions are XOR dominated, efficient AND-XOR decomposition can lead to more compact realization of such circuits [1], Amongst the AND-XOR logic expressions, although there are several classes [1] viz. RM, PPRM, FPRM, KRO, PSDKRO, GRM and ESOP, ESOPs are the most general Reed-Muller forms with interesting properties. Practically speaking, they have numerous applications in synthesis and design-for-test [3]. This work extends the originally proposed method of [1] [4], addressing the problem of ESOP minimization, by adding simple algebraic factorization operations. Besides, with new binary matrices of order ´2 times n´, we illustrate how to simplify even irreducible ESOP forms. We make it clear that XOR (XNOR) intensive combinational logic could effectively be implemented using five types of logic gates, namely XOR XNOR, NAND, NOR and NOT, in comparison with some of the solutions obtained in [10] [11]. The proposed synthesis solution is quantitatively evaluated on the basis of power consumption metric, after technology-mapping based on static CMOS logic style, with a 0.35 micron TSMC process technology.
Keywords :
combinational circuits; logic design; logic gates; low-power electronics; matrix algebra; minimisation; network synthesis; AND-OR logic; AND-XOR logic expressions; ESOP minimization; TSMC process technology; XOR-XNOR intensive combinational logic; algebraic factorization; binary matrices; combinational functions; combinational logic synthesis; efficient AND-XOR decomposition; low power synthesis; power consumption metric; static CMOS logic; technology mapping; CMOS logic circuits; CMOS technology; Circuit synthesis; Design for testability; Energy consumption; Logic design; Logic devices; Logic gates; Logic programming; Minimization methods;
