Efficient scan-path and BIST latches for static CMOS ASIC circuits

The authors present a scan-path and BIST (built-in self test) implementation scheme evolved to reduce the cost of incorporating testability in a CMOS ASIC (application specific integrated circuit) environment. Minimal penalty on circuit performance, low area overhead and ease of design are the main goals, achieved by taking into account CMOS semicustom design specific conditions. Scan-path and BIST latches are designed to have minimal impact on normal latch performance. Design independence is achieved by using an independent clock for testing, while area overhead is reduced by careful use of MOS gates and dynamic latching stages to incorporate testability in an otherwise fully static and complementary CMOS environment