Design Considerations for Sub-mW RF CMOS Low-Noise Amplifiers

Design considerations for sub-mW fully integrated narrow-band RF CMOS low-noise amplifiers (LNAs) are presented. The impacts of device-level properties and biasing on gain, noise, linearity, and power consumption of an LNA are discussed. Based on the design trade-offs discussed in the paper, a cascode LNA is designed and simulated in a standard 90 nm CMOS process to operate in the 2.4 GHz band. The LNA achieves a voltage gain of 22.7 dB, NF of 2.8 dB, IIP3 of +5.14 dBm, and PldB of -10 dBm, while consuming 943 muW from a 1 V supply.