A memory controller for mapping an array of circular buffers into a RAM

Author

Godon, F. ; Al-Khalili, D. ; Inkol, R.

Author_Institution

Dept. of Electr. & Comput. Eng., R. Mil. Coll. of Canada, Kingston, Ont., Canada

fYear

1990

fDate

12-14 Aug 1990

Firstpage

645

Abstract

A 1.5-μm CMOS ASIC with a total complexity of over 22000 gates has been developed to generate and keep track of the offsets within 32 circular buffers. It offers a fair arbitration of interleaved read/write operations at a maximum data transfer rate of 20 MHz. Although the device is intended for a specialized electronic warfare system application, the design features incorporated make it generic and suitable for other applications such as communications interfaces in multiprocessor systems

Keywords

CMOS integrated circuits; VLSI; application specific integrated circuits; buffer storage; cellular arrays; electronic warfare; random-access storage; storage management chips; 1.5 micron; 20 Mbit/s; CMOS ASIC; arbitration of interleaved read/write operations; buffers mapping into RAM; circular buffer memory controller; communications interfaces; data transfer rate; electronic warfare system; gate arrays; multiprocessor systems; Buffer storage; Computer architecture; Counting circuits; Military computing; Physics computing; Process control; Radar; Random access memory; Read-write memory; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1990., Proceedings of the 33rd Midwest Symposium on

Conference_Location

Calgary, Alta.

Print_ISBN

0-7803-0081-5

Type

conf

DOI

10.1109/MWSCAS.1990.140801

Filename

140801