Optimizing the Stage Resolution in Pipelined SAR ADCs for High-Speed High-Resolution Applications

The successive approximation register (SAR) analog-to-digital converters (ADCs) outperform other types of ADCs on the area and energy efficiency due to its binary searching algorithm, which however has a conversion speed limitation. When pipelining multiple SAR ADCs, the speed is improved, the resolutions in individual stages are relaxed, and the nonidealities from non-first stages are desensitized by the gains preceding them. This brief examines the effects of the stage resolution on linearity, noise, speed, area, and power consumption in pipelined SAR ADCs. Two conclusions are reached. First, under certain cases, a larger resolution per stage improves the ADC linearity without costing the speed of the operational amplifiers (op-amps) used for residue amplifications. However, the stage resolution does not affect the op-amp open-loop gain requirement. Second, for area and power consideration, allocating about one quarter of the overall number of bits to the first stage is optimum in the practical situation that the area and power of the active circuitries are tens or hundreds of times of those of the unit capacitors in the SAR sub-ADCs.