DocumentCode :
2810779
Title :
“Managing process variance in analog designs”
Author :
Atwood, Eugene
Author_Institution :
IBM
fYear :
2012
fDate :
5-8 Nov. 2012
Firstpage :
1
Lastpage :
1
Abstract :
Methods to manage the effect of process normal and process variance on analog circuit designs have driven significant invention within the analog design community. Has test kept up with ensuring outgoing quality? The application of digital algorithms, which control various types of trimming devices, has enabled built in self-calibration (BISC) of sophisticated analog functions. High speed serial applications, phase locked loops, analog-to-digital converters, low voltage amplifiers and digital radios all benefit from improvements to their respective signal-to-noise ratios. In the very large scale integrated digital design space, embedded analog monitors are used to support optimization of power-performance metrics by adjustments to clock tree timing, power supply domain voltage adjustments and circuit redundancy. Memories benefit from redundancy and are a true mixed signal analog design, relying on sophisticated sense amplifiers. All integrated circuits are based on analog circuit behaviors influenced by process variance. Analog functions continue to be specification tested, which has it´s own unique coverage issues, but what about the supporting digital circuitry, analog calibration circuitry and redundant logic circuitry? “Who is watching the watchers?” How often is calibration circuitry used? Calibration and redundant circuitry are subject to aging and reliability issues. What needs to be considered in managing these issues? Can useful process feedback information be developed from manufacturing test use of BISC results? Are some calibrations required to be traceable to a standard? How is the relationship managed between analog designers and manufacturing test? Are test access port standards exploited or are ad-hoc access methods used? What can be done to improve the engineering design automation (EDA) environment? Panelists will be asked to present a specific application (case study.) The case study should describe the EDA environment, design/te- t development flow, the method of BISC or other tuning application and finally manufacturing test application and coverage. Panelists will each be asked to provide an “axiom” intended to provide guidance to engineers working in the area of calibration.
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Test Conference (ITC), 2012 IEEE International
Conference_Location :
Anaheim, CA, USA
ISSN :
1089-3539
Print_ISBN :
978-1-4673-1594-4
Type :
conf
DOI :
10.1109/TEST.2012.6401527
Filename :
6401527
Link To Document :
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