Title :
Using Hardware Acceleration to Reduce FPGA Placement Times
Author :
Fobel, Christian ; Gréwal, Gary ; Morton, Andrew
Author_Institution :
Univ. of Guelph, Guelph
Abstract :
Placement is one of the most time-consuming processes in automatically synthesizing and configuring circuits for field programmable gate arrays (FPGAs). In this paper, we present a hardware-accelerated iterative-improvement algorithm for performing placement. The design and evaluation of the accelerated algorithm is presented. Initial results indicate speedups of 3.5 times of hardware over software execution times. By taking better advantage of hardware parallelism, it is anticipated that speedups of at least an order of magnitude can be accomplished.
Keywords :
field programmable gate arrays; iterative methods; logic design; FPGA placement time; field programmable gate array; hardware-accelerated iterative-improvement algorithm; Acceleration; Algorithm design and analysis; Field programmable gate arrays; Hardware; Integrated circuit interconnections; Iterative algorithms; Logic arrays; Parallel processing; Routing; Switches;
Conference_Titel :
Electrical and Computer Engineering, 2007. CCECE 2007. Canadian Conference on
Conference_Location :
Vancouver, BC
Print_ISBN :
1-4244-1020-7
Electronic_ISBN :
0840-7789
DOI :
10.1109/CCECE.2007.166