Wirelength Based Clustering Technique for VLSI Physical Design

Physical design of Very Large Scale Integrated (VLSI) circuits is the phase where the physical shape of a circuit is decided. Layout is part of the physical design step where the locations of all circuit components and their wiring are decided. Layout typically consists of 3 stages: partitioning, placement, and routing. The main focus of this research is on the placement step. There are various efficient and effective academic placement tools. However, most of the placers ignore the global nets, long wires that span entire rows or columns of a circuit. Usually the global nets make up 10% of the total nets, but can comprise up to 50% of the total wirelength. In this work, a new clustering algorithm is designed to reduce the length of global nets. This new clustering algorithm clusters cells belonging to a global net if they have any other connections. The algorithm has been tested on ICCAD04 benchmark suite. The experimental results show that the total wirelength can be reduced for some test benchmarks by up to 8%.