Title :
A unified method for parametric fault characterization of post-bond TSVs
Author :
Yu-Hsiang Lin ; Shi-Yu Huang ; Kun-Han Tsai ; Wu-Tung Cheng ; Sunter, Sedat
Author_Institution :
Electr. Eng. Dept., Nat. Tsing Hua Univ., Hsinchu, Taiwan
Abstract :
A TSV in a 3D IC could suffer from two major types of parametric faults - a resistive open fault, or a leakage fault. Dealing with these parametric faults (which do not destroy the functionality of a TSV completely but only degrade its quality or performance) is often trickier than dealing with a stuck-at fault. Previous works have not proposed a unified test structure and method that can characterize their respective effects. Based on our previous test structure, called VOT (Variable Output Threshold) scheme for delay faults, we propose a unified in-situ characterization flow for both parametric fault types of a post-bond TSV. With this flow, one can easily derive a more insightful assessment of a parametric fault in production test, process monitoring, and/or diagnosis-driven yield learning.
Keywords :
design for testability; fault diagnosis; integrated circuit testing; three-dimensional integrated circuits; 3D IC; VOT; delay fault; design for testability; diagnosis-driven yield learning; leakage fault; parametric fault characterization; postbond TSV; process monitoring; production test; resistive open fault; stuck-at fault; unified in-situ characterization flow; unified test structure; variable output threshold scheme; Circuit faults; Delay; Inverters; Oscillators; Propagation delay; Testing; Through-silicon vias; 3D IC; Characterization; Design for Testability; Leakage Fault; Parametric Fault; Resistive Open Fault; Through-Silicon Via;
Conference_Titel :
Test Conference (ITC), 2012 IEEE International
Conference_Location :
Anaheim, CA
Print_ISBN :
978-1-4673-1594-4
DOI :
10.1109/TEST.2012.6401566