Implementation of Low Power and High-Speed Higher Order Channel Filters for Software Radio Receivers

The most computationally intensive part of the wideband receiver of a software defined radio (SDR) is the channelizer since it operates at the highest sampling rate. Higher order FIR channel filters are needed in the channelizer to meet the stringent adjacent channel attenuation specifications of wireless communications standards. In this paper, we present a coefficient-partitioning algorithm for realizing low power and high-speed channel filters. Design examples of the channel filters employed in the digital advanced mobile phone system (D-AMPS) and personal digital cellular (PDC) receivers show that the average reductions of memory and power consumption achieved using our method over existing method are 25% and 50% respectively