The impact of the gate dielectric quality in developing Au-free D-mode and E-mode recessed gate AlGaN/GaN transistors on a 200mm Si substrate

The selection of the gate dielectric is one of the most critical stability issues in recessed gate AlGaN/GaN transistors. In this work, we show that the quality of the gate dielectric has a strong impact on: 1) the threshold voltage (V_TH) hysteresis, 2) the drain current reduction for enhancement mode devices, and 3) the forward gate bias TDDB (time dependent dielectric breakdown). It will be shown that the V_TH hysteresis and the current reduction can be minimized by using a dielectric with lower interface state density (D_it) and less border traps, e.g., a PE-ALD SiN dielectric. Furthermore, the 0.01% failures at 20 years TDDB requirement at 150°C for a large power device, e.g., gate width Wg=36mm, necessitates the use of at least a 25nm-thick PE-ALD SiN gate dielectric.