Title :
An advanced p-channel LDMOS FET with HTRB tolerability of high-voltage pulse transmitter ICs for ultrasound applications
Author :
Miyoshi, Tomoyuki ; Wada, Shinichiro ; Shinomiya, Toshio ; Ueno, Satoshi
Author_Institution :
Central Res. Lab., Hitachi Ltd., Hitachi, Japan
Abstract :
Novel +/-100-V p-channel LDMOS FET technology were developed for a pulse transmitter IC for an ultrasound application. With a design of steep-profile in drift region for a higher RESURF effect, area efficiency of the output performance can be improved by 20 % of Ron, sp. By an optimization of gate poly-Si structure for reducing electric field and higher tolerability against electron trapping in LOCOS, stable performance against high-temperature reverse bias (HTRB) can be obtained. BVoff/Ron, sp of 260 V/3079 ohm·mm2 of p-channel LDMOS and well matched ID-VDS curve traces between n-channel and p-channel LDMOS FETs enabled the suitable bipolar pulse mirror symmetry with less than -40 dBc of second harmonic distortion in the IC with long-term stability.
Keywords :
high-temperature electronics; power MOSFET; ultrasonic devices; HTRB tolerability; LOCOS; RESURF effect; advanced p-channel LDMOS FET; area efficiency; bipolar pulse mirror symmetry; drift region; electric field reduction; gate poly-silicon structure optimization; high-temperature reverse bias; high-voltage pulse transmitter IC; output performance; steep-profile design; ultrasound applications; Electric fields; Field effect transistors; Integrated circuits; Logic gates; Stress; Transmitters; Ultrasonic imaging; HTRB; RESURF; p-channel LDMOS;
Conference_Titel :
Power Semiconductor Devices & IC's (ISPSD), 2015 IEEE 27th International Symposium on
Conference_Location :
Hong Kong
Print_ISBN :
978-1-4799-6259-4
DOI :
10.1109/ISPSD.2015.7123472
