DocumentCode
2812945
Title
IC modeling for yield-aware design with variable defect rates
Author
Kumar, Vinu Vijay ; Lach, John
Author_Institution
Dept. of Electr. & Comput. Eng., Virginia Univ., Charlottesville, VA, USA
fYear
2005
fDate
Jan. 24-27, 2005
Firstpage
489
Lastpage
495
Keywords
FIR filters; failure analysis; integrated circuit design; integrated circuit testing; IC modeling; benchmark FIR filter design; combinatorial model; component failure; defect rate; design tradeoff; expected quality; semiconductor burn-in test; yield-aware design; Circuit testing; Fabrication; Integrated circuit modeling; Integrated circuit technology; Integrated circuit testing; Integrated circuit yield; Process design; Semiconductor device manufacture; Semiconductor process modeling; Throughput;
fLanguage
English
Publisher
ieee
Conference_Titel
Reliability and Maintainability Symposium, 2005. Proceedings. Annual
ISSN
0149-144X
Print_ISBN
0-7803-8824-0
Type
conf
DOI
10.1109/RAMS.2005.1408410
Filename
1408410
Link To Document