Designing efficient Benes and Banyan based input-buffered ATM switches

Multistage network based input-buffered ATM switches, which have been studied extensively, are cheaper compared to crossbar designs but suffer from elaborate cell selection methods or expensive network setup. In this paper, a fast cell selection method is proposed to avoid slow cell selection and costly network setup for these designs. In particular, we propose network hardware specific selection techniques for cell selection in input buffered Banyan network with an internal speed twice that of the external links. Our simulation results show that cell selection by looking at up to 10 cells in each input queue for switch sizes up to N=64 yields 95% or higher switch utilization