Quantitative Evaluation of Low Density Parity Check Convolutional Code Encoder and Decoder Algorithms for the XInC MIMD Multithreaded Microprocessor

In this paper, we introduce low density parity check convolutional code (LDPC-CC) parallel encoder and decoder algorithms for the XInC MIMD multi-threaded microprocessor. A modified memory-based decoder architecture and an interleaved LDPC-CC code scheme are also proposed. Extensions and simple modifications to the current XInC microprocessor are proposed to decrease the number of instruction cycles per decoded bit. A XInC emulator was built to evaluate and quantify the hardware utilization and performance benefits of these modifications and other alternatives.