Implementation of LDPC Decoder in DVB-S2 Using Min-Sum Algorithm

Author

Jeong, Haeseong ; Kim, Jong Tae

Author_Institution

Sch. of Inf. & Commun. Eng., Sungkyunkwan Univ., Suwon

fYear

2008

fDate

28-30 Aug. 2008

Firstpage

359

Lastpage

362

Abstract

A new market on digital broadcasting is opening because of the adoption of digital video broadcasting second generation as a digital broadcasting standard in Europe. The DVB-S2 uses a low density parity check, so DVB-S2 has much fast communication speed than conventional DVB which uses Reed-Solomon code and convolutional code for error correction. In this paper, we valuate performance and implement LDPC decoder of FEC which is important sub-system of DVB-S2 using VHDL. The simulated and implemented LDPC decoder is based on the min-sum algorithm.

Keywords

decoding; digital video broadcasting; forward error correction; hardware description languages; parity check codes; DVB-S2; LDPC decoder; VHDL; communication speed; digital broadcasting standard; digital video broadcasting; forward error correction; low density parity check; min-sum algorithm; Broadcast technology; Decoding; Digital video broadcasting; Forward error correction; Modulation coding; Parity check codes; Quadrature phase shift keying; Reed-Solomon codes; Satellite broadcasting; Sparse matrices;

fLanguage

English

Publisher

ieee

Conference_Titel

Convergence and Hybrid Information Technology, 2008. ICHIT '08. International Conference on

Conference_Location

Daejeon

Print_ISBN

978-0-7695-3328-5

Type

conf

DOI

10.1109/ICHIT.2008.193

Filename

4622852