DocumentCode
2813731
Title
Latchup in CMOS technology
Author
Hargrove, M.J. ; Voldman, S. ; Gauthier, R. ; Brown, J. ; Duncan, K. ; Craig, W.
Author_Institution
IBM Semicond. Res. & Dev. Center, Hopewell Juction, NY, USA
fYear
1998
fDate
March 31 1998-April 2 1998
Firstpage
269
Lastpage
278
Abstract
This paper is a review of the latchup phenomena in past and present CMOS technologies. Both static and transient characterization techniques are described, as well as process related solutions and layout ground rule constraints. Technology scaling implications are discussed in the context of latchup holding voltage/current and minimum N/sup +/ to P/sup +/ spacing.
Keywords
CMOS integrated circuits; doping profiles; integrated circuit layout; integrated circuit reliability; integrated circuit testing; transient analysis; CMOS technology; latch-up holding current; latch-up holding voltage; latch-up phenomena; layout ground rule constraints; minimum N/sup +/-P/sup +/ spacing; process related solutions; static characterization techniques; technology scaling; transient characterization techniques; CMOS technology; Coupling circuits; Impedance; Inverters; Microelectronics; Power supplies; Research and development; Space technology; Substrates; Switches;
fLanguage
English
Publisher
ieee
Conference_Titel
Reliability Physics Symposium Proceedings, 1998. 36th Annual. 1998 IEEE International
Conference_Location
Reno, NV, USA
Print_ISBN
0-7803-4400-6
Type
conf
DOI
10.1109/RELPHY.1998.670561
Filename
670561
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