Design of PLC timer system based on FPGA

Aiming at the design of the small PLC timer system, based on the analysis of operational characteristics of PLC timer and the process of PLC user timer program and the data transmission requirements of PLC user program execution module and the timer, a method which applies the FPGA Parallel algorithm to designing small PLC timer system, is presented. The timer system is composed of clock generator unit, timing unit, timing control unit and the chip select circuit. While the timer runs at the speed of 1ms timed pulse, the operation of timer is translated into the operation of RAM memory cell which is made up of FPGA. That makes user can operate on RAM memory cell instead of the timer, and it just take up a few execution time of PLC user program. This paper introduces the theory and structure of the FPGA timer system, the state transition diagram of timer control module, the timing diagram of user program execution module operating on timer, finally take an experiment and gives analysis of the results.