Title :
Synchronous versus asynchronous adders
Author :
Abuelyaman, Eltayeb S. ; ShankarReddy, Poornima Y.
Author_Institution :
Dept. of Electr. Eng., Western Michigan Univ., Kalamazoo, MI, USA
Abstract :
Despite the fact that most clock-related problems have been resolved, speeding-up the execution cycle has yet to be optimized. One way to achieve this is by having the components and modules of a microprocessor communicate in an asynchronous mode. A survey of several programs varying in length and application indicates that addition is the most frequently used instruction. Consequently, the design of asynchronous adders is evaluated
Keywords :
adders; combinatorial circuits; digital arithmetic; logic design; asynchronous adders; asynchronous mode; execution cycle speed-up; logic design; Adders; Assembly; Circuits; Clocks; Frequency; Logic gates; Microprocessors; Propagation delay; Protocols; Stability;
Conference_Titel :
Circuits and Systems, 1990., Proceedings of the 33rd Midwest Symposium on
Conference_Location :
Calgary, Alta.
Print_ISBN :
0-7803-0081-5
DOI :
10.1109/MWSCAS.1990.140848
