10 K gate GaAs JFET sea of gates

Author

Kawasaki, H. ; Wada, M. ; Hida, Y. ; Takano, C. ; Kashahara, J.

Author_Institution

Sony Corp. Res. Center., Yokohama, Japan

fYear

1990

fDate

7-10 Oct. 1990

Firstpage

135

Lastpage

138

Abstract

A GaAs 10 K-gate sea-of-gates IC has been successfully fabricated using JFETs with a gate length of 0.5 mu m. A basic cell is designed to constitute both a DCFL (directly coupled FET logic) 4-NOR circuit and an SCFL (source coupled FET logic) inverter circuit with the identical enhancement-type JFET. Each input and output level is designed to be compatible with Si ECL, CMOS, and TTL logic levels. The unloaded and loaded DCFL gate delays are 21 ps/gate and 180 ps/gate with power consumption of 0.4 mW/gate and 0.5 mW/gate, respectively. The toggle frequency of a T-type flip-flop is 3.9 GHz and 4.4 GHz for DCFL and SCFL, respectively. The basic performance of the 10 K-gate GaAs JFET sea-of-gates IC is discussed.<>

Keywords

field effect integrated circuits; flip-flops; gallium arsenide; invertors; junction gate field effect transistors; logic arrays; 0.5 micron; 3.9 GHz; 4-NOR circuit; 4.4 GHz; DCFL; GaAs; JFET sea of gates; SCFL; T-type flip-flop; gate delays; gate length; input level; inverter circuit; output level; power consumption; toggle frequency; CMOS logic circuits; Coupling circuits; Delay; Energy consumption; FETs; Gallium arsenide; JFET circuits; Logic circuits; Logic design; Pulse inverters;

fLanguage

English

Publisher

ieee

Conference_Titel

Gallium Arsenide Integrated Circuit (GaAs IC) Symposium, 1990. Technical Digest 1990., 12th Annual

Conference_Location

New Orleans, LA, USA

Type

conf

DOI

10.1109/GAAS.1990.175469

Filename

175469