Title :
FET-FET logic: a high performance, high noise margin E/D logic family
Author :
LaRue, G. ; Williams, T. ; Chan, P.
Author_Institution :
Boeing Aerospace & Electronics, Seattle, WA, USA
Abstract :
A new logic family, FFL (FET-FET logic), is reported which combines a low leaded delay-power product with good noise margin. It has many desirable attributes for GaAs VLSI circuits. Measurements of FFL and six other logic families in enhancement/depletion MESFET technology are compared for speed, power, and noise margin and show the advantages of using FFL for many applications. FFL requires only a single 2-V power supply, performs single-ended complex logic functions, and can operate reliably over the military temperature range.<>
Keywords :
VLSI; field effect integrated circuits; integrated logic circuits; 2 V; E/D logic family; FET-FET logic; FFL; GaAs; VLSI circuits; enhancement/depletion MESFET technology; high noise margin; high performance; military temperature range; power; single 2-V power supply; single-ended complex logic functions; speed; Circuit noise; Delay; Gallium arsenide; Logic; MESFETs; Noise measurement; Power measurement; Power supplies; Velocity measurement; Very large scale integration;
Conference_Titel :
Gallium Arsenide Integrated Circuit (GaAs IC) Symposium, 1990. Technical Digest 1990., 12th Annual
Conference_Location :
New Orleans, LA, USA
DOI :
10.1109/GAAS.1990.175492
