FPGA-based multi-channel CRC generator implementation

Author

Jun, Yang ; Jun, Ding ; Na, Li ; Yixiong, Guo ; Yin, Dong

Author_Institution

Sch. of Inf. Sci. & Eng., Yunnan Univ., Kunming, China

Volume

1

fYear

2010

fDate

17-18 April 2010

Firstpage

81

Lastpage

84

Abstract

This article mainly describes a way of designing a parallel and highly pipelined Cyclic Redundancy Code (CRC) generator. The design can handle five different channels at an input rate of 2Gbps each. The generated CRCS are compatible with the 32-bit Ethernet standards. This circuit has been implemented with the chip EP2C35F672C6 of ALTERA using the properties of Galois Field. The synthesis results show that the design can meet the needs of high-speed data integrity check.

Keywords

Galois fields; codecs; cyclic redundancy check codes; data communication equipment; field programmable gate arrays; local area networks; ALTERA EP2C35F672C6 chip; Ethernet standard; FPGA; Galois field; high speed data integrity check; multichannel CRC generator implementation; pipelined cyclic redundancy code; word length 32 bit; Cyclic redundancy check; Equations; Error correction; Ethernet networks; Feedback circuits; Galois fields; Hardware; Linear feedback shift registers; Polynomials; Software algorithms; 10Gbps Ethernet; CRC; FPGA; Galois Fields;

fLanguage

English

Publisher

ieee

Conference_Titel

E-Health Networking, Digital Ecosystems and Technologies (EDT), 2010 International Conference on

Conference_Location

Shenzhen

Print_ISBN

978-1-4244-5514-0

Type

conf

DOI

10.1109/EDT.2010.5496514

Filename

5496514