Architectural design features of a programmable high throughput AES coprocessor

Author

Hodjat, Alireza ; Schaumont, Patrick ; Verbauwhede, Ingrid

Author_Institution

Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA

Volume

2

fYear

2004

fDate

5-7 April 2004

Firstpage

498

Abstract

Programmable, high throughput domain specific crypto processors are required for different networking applications. We present the architectural design features that lead to a multiple Gbits/s rate AES coprocessor, which is programmable with domain specific instructions for Gbit throughput IPSec and other applications. Our design is a loosely coupled, independently working crypto-coprocessor that runs AES in ECB, CBC-MAC, Counter, and CCM modes of operation at a maximum throughput of 3.43 Gbits/s in a 0.18 μm CMOS technology without any penalty in throughput for any of the above modes.

Keywords

CMOS integrated circuits; coprocessors; cryptography; instruction sets; parallel architectures; pipeline processing; 0.18 μm CMOS technology; CBC-MAC mode; CCM mode; Counter mode; ECB mode; architectural design features; high throughput domain specific crypto processors; programmable high throughput AES coprocessor; Assembly; CMOS technology; Clocks; Coprocessors; Counting circuits; Cryptography; Ethernet networks; Security; Throughput; Virtual private networks;

fLanguage

English

Publisher

ieee

Conference_Titel

Information Technology: Coding and Computing, 2004. Proceedings. ITCC 2004. International Conference on

Print_ISBN

0-7695-2108-8

Type

conf

DOI

10.1109/ITCC.2004.1286703

Filename

1286703