Self-checking ripple-carry adder with Ambipolar Silicon NanoWire FET

Author

Turkyilmaz, O. ; Clermidy, F. ; Amaru, Luca Gaetano ; Gaillardon, Pierre-Emmanuel ; De Micheli, G.

Author_Institution

CEA-LETI, Grenoble, France

fYear

2013

fDate

19-23 May 2013

Firstpage

2127

Lastpage

2130

Abstract

For the rapid adoption of new and aggressive technologies such as ambipolar Silicon NanoWire (SiNW), addressing fault-tolerance is necessary. Traditionally, transient fault detection implies large hardware overhead or performance decrease compared to permanent fault detection. In this paper, we focus on on-line testing and its application to ambipolar SiNW. We demonstrate on self-checking ripple-carry adder how ambipolar design style can help reduce the hardware overhead. When compared with equivalent CMOS process, ambipolar SiNW design shows a reduction in area of at least 56% (28%) with a decreased delay of 62% (6%) for Static (Transmission Gate) design style.

Keywords

adders; bipolar transistors; elemental semiconductors; fault tolerance; field effect transistors; integrated circuit testing; nanowires; silicon; Si; ambipolar design; ambipolar nanowire FET; equivalent CMOS process; fault-tolerance; online testing; self-checking ripple-carry adder; static design style; transient fault detection; transmission gate; Adders; CMOS integrated circuits; Circuit faults; Logic gates; Silicon; Testing; Transistors;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems (ISCAS), 2013 IEEE International Symposium on

Conference_Location

Beijing

ISSN

0271-4302

Print_ISBN

978-1-4673-5760-9

Type

conf

DOI

10.1109/ISCAS.2013.6572294

Filename

6572294