High-throughput hardware-efficient soft-input soft-output MIMO detector for iterative receivers

This paper presents a high-throughput, hardware-efficient iterative soft-input soft-output signal detector for spatial-multiplexing system. The detector provides near-optimal performance with much reduced complexity by adopting imbalanced tree-travel strategy, LLR correction techniques, and iteration-adaptive node-selection method. A multi-stage highly-parallel VLSI architecture is employed to implement the detection algorithm. In a 65-nm CMOS technology, the detector occupies 0.64 mm² core area and shows a peak throughput of 1.2 Gb/s. The energy consumed in the proposed detector is 116.5 pJ/b.