DocumentCode :
2816904
Title :
Multidimensional Householder based high-speed QR decomposition architecture for MIMO receivers
Author :
Kurniawan, Iput Heri ; Ji-Hwan Yoon ; Jongsun Park
Author_Institution :
Sch. of Electr. Eng., Korea Univ., Seoul, South Korea
fYear :
2013
fDate :
19-23 May 2013
Firstpage :
2159
Lastpage :
2162
Abstract :
Conventional QR decomposition (QRD) hardware with a large size of channel matrix suffers from very low throughput and large latencies. This paper presents a high speed multi-dimensional (M-D) coordinate rotation digital computer (CORDIC) based QRD architecture. The novel high speed M-D architecture is enabled by exploiting multiple annihilations in a single CORDIC operation and removing data dependencies between two CORDIC operations (evaluation and application CORDIC) in Householder-based QRD process. The proposed QRD architecture can compute 4×4 complex R matrix for every 8 clock cycles. Our QRD hardware for 4×4 channel matrix was implemented using Samsung 0.13μm CMOS process, and the experimental results show that the proposed architecture achieves 4.74x speed-up compared to the conventional hybrid M-D based QRD.
Keywords :
CMOS integrated circuits; MIMO communication; digital arithmetic; matrix decomposition; radio receivers; signal processing; wireless channels; MD CORDIC; MIMO receiver; QRD; Samsung CMOS process; channel matrix; high-speed QR decomposition hardware architecture; multidimensional coordinate rotation digital computer; multidimensional householder; size 0.13 mum; Clocks; Computer architecture; Hardware; MIMO; Matrix decomposition; Receivers; Vectors;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems (ISCAS), 2013 IEEE International Symposium on
Conference_Location :
Beijing
ISSN :
0271-4302
Print_ISBN :
978-1-4673-5760-9
Type :
conf
DOI :
10.1109/ISCAS.2013.6572302
Filename :
6572302
Link To Document :
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