III-V/Si heterojunctions for steep subthreshold-slope transistor

Main target in future LSI is to achieve low power consumption while enhancing performance. There are many concerns to lower the power consumption in recent CMOS technologies, such as multi-gate architecture for suppressing short-channel effect and OFF-state leakage current. The state-of-the-art FET offered by the gate structure surely reduces the power dissipation, but the power-scaling will be limited by FET in itself since the reduction in supply voltage in Si-based MOSFETs has some difficulties, such as low carrier mobility under lower electrical field and physically limited subthreshold slope (SS). Especially, utilization of steep subthreshold-slope transistor such as tunnel FETs (TFETs) and impact ionization FETs is important for the low power circuits because physical limitation due to carrier thermal diffusion stops a scaling of the power consumption even if the multi-gate structure and III-Vs are utilized. Thus, another channel materials and transport mechanisms should be addressed mutually in CMOS technologies, and these distinct features should possess good compatibility with the Si-based CMOS. In this regard, heterojunctions formed across the III-V nanowire (NW) and Si would be promising building blocks for the future extended CMOS technologies. Here, we present integration of III-V nanowires on Si by selective-area growth and concept for steep SS transistor using III-V nanowire/Si heterojunctions.