Full-quantum simulation of heterojunction TFET inverters providing better performance than multi-gate CMOS at sub-0.35V VDD

Tunnel FETs (TFETs) are promising alternatives to the conventional CMOS technology for steeper-than-60mV/dec subthreshold slopes (SS) required to limit power consumption of integrated circuits [1]. Current challenges for TFET integration into practical circuit applications include reaching acceptable I_ON levels, suppressing ambipolar effects, improving output characteristics [2], and simultaneously co-integrating optimized n-and p-type devices. All of these issues are carefully taken into account in this work. Device- and circuit-level design of TFET inverters is proposed, based on co-optimized n-and p-type TFETs integrated on the same InAs/ Al_0.05Ga_0.95Sb platform. A full-band quantum simulation approach is adopted to properly account for quantum effects which strongly influence TFET device, and hence circuit, performance. This advances the state of the art of TFET-based circuit literature, which is mostly based on simplified TCAD models [3], with rare calibrations against atomistic calculations [4].