Highly parallel increment/decrement using CMOS technology

Author

Hashemian, Reza

Author_Institution

Dept. of Electr. Eng., Northern Illinois Univ., DeKalb, IL, USA

fYear

1990

fDate

12-14 Aug 1990

Firstpage

866

Abstract

A design technique for the construction of an incrementer/decrementer circuit is presented. The technique is shown to be highly efficient both in terms of space and time. There are two basic operations involved in this technique: (1) finding the least significant zero bit (LSZB), and (2) inverting all bits below LSZB including LSZB. For the first part, a network of priority resolution (PR) modules is implemented which is new in structure, and the modules operate concurrently. For the second part, selector modules which produce inverted or non-inverted bits, depending on the selector code value, are used. A 64-bit incrementer circuit is being designed using MOSIS CMOS3 technology. The simulation result of the proposed design is encouraging and indicates the high efficiency of the device

Keywords

CMOS integrated circuits; integrated logic circuits; 64-bit incrementer circuit; CMOS; MOSIS CMOS3 technology; efficiency; incrementer/decrementer circuit; inverting; least significant zero bit; operations; priority resolution modules; selector modules; Adders; Binary trees; CMOS technology; Circuit simulation; Concurrent computing; Delay effects; Hardware; Investments; Signal resolution; Space technology;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1990., Proceedings of the 33rd Midwest Symposium on

Conference_Location

Calgary, Alta.

Print_ISBN

0-7803-0081-5

Type

conf

DOI

10.1109/MWSCAS.1990.140858

Filename

140858