Title :
A single SAR ADC converting multi-channel sparse signals
Author :
Wenjuan Guo ; Youngchun Kim ; Sanyal, Amit ; Tewfik, Ahmed ; Nan Sun
Author_Institution :
Dept. of Electr. & Comput. Eng., Univ. of Texas at Austin, Austin, TX, USA
Abstract :
This paper presents a simple but high performance architecture for multi-channel analog-to-digital conversion. Based on compressive sensing, only one SAR ADC is needed to convert multi-channel sparse inputs, leading to significant analog power saving and hardware saving. Moreover, it helps avoid problems occurring in conventional multi-channel ADCs such as timing skew, offset mismatch, and gain mismatch. A 12-bit SAR ADC converting 4-channel sparse signals simultaneously is designed in 130nm CMOS process. The design reaches a SNDR of 66.3dB and consumes an average power of 58μW at the sampling frequency of 1MHz. The L1 minimization method is chosen to reconstruct the input signals. The single-tone and multi-tone inputs can be reconstructed with a minimum precision of 68dB and 55dB THD, respectively.
Keywords :
CMOS digital integrated circuits; analogue-digital conversion; compressed sensing; integrated circuit design; signal reconstruction; 4-channel sparse signals; CMOS process; SAR ADC conversion; SNDR; THD; analog power saving; compressive sensing; frequency 1 MHz; hardware saving; high performance architecture; multichannel analog-to-digital conversion; multichannel sparse signals; power 58 muW; sampling frequency; signal reconstruction; size 130 nm; storage capacity 12 bit; Analog-digital conversion; Bandwidth; Capacitors; Computer architecture; Frequency division multiplexing; Hardware; Noise;
Conference_Titel :
Circuits and Systems (ISCAS), 2013 IEEE International Symposium on
Conference_Location :
Beijing
Print_ISBN :
978-1-4673-5760-9
DOI :
10.1109/ISCAS.2013.6572321