Three-level boost rectifier with FPGA digital control

This paper presents a three-state switching cell single-phase three-level boost rectifier with Power Factor Correction (PFC) using FPGA digital control. Its main features are: reduced conduction losses, weight and volume; simple digital control strategy based on One-Cycle Control (OCC) technique using FPGA; connection between input and output enabling the use of inverter and bypass for UPS application. A theoretical analysis, simulation results and preliminaries experimental results from a 3kW lab model are presented. The FPGA used in this study is an ALTERA Cyclone II EP2C20F484C7.