Device Behavior Modeling for Carbon Nanotube Silicon-On-Insulator MOSFETs

We offer a methodology for the numerical analysis of carbon nanotube (CNT) embedded silicon-on-insulator (SOI) MOSFETs. We examine CNT-SOI-MOSFETs that have a planar sheet of single-walled zig-zag semiconducting CNTs embedded along the channel direction, as shown in Fig. 1. To obtain device performance details including current-voltage characteristics, we employ a quantum based device solver [l] along with a Monte Carlo simulator [2]. Our calculated results show that replacing the silicon with CNTs in the channel may significantly improve device performance. The CNT-SOI-MOSFET with the smallest diameter tube may surpass other configurations of CNT-SOI-MOSFETs and conventional SOI-MOSFET in performance if fabricated successfully with the same channel thickness. In addition, under certain conditions the CNT-SOI-MOSFETs show negative differential resistance.